With a view to achieving higher integration and higher performance of a semiconductor device, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (as disclosed, for example, in Patent Document 1: JP 2-188966A). In the SGT, a source, a gate and a drain are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor.
In cases where an LSI (large-scale integration) circuit is made up using an SGT, it is essential to employ an SRAM comprising a combination of a plurality of SGTs, as a cache memory for the LSI circuit (the SRAM will hereinafter be referred to as “SGT-SRAM”). In recent years, there is an extremely strong need for increasing a capacity of an SRAM to be mounted on an LSI circuit. Thus, it is necessary to achieve an SRAM having a sufficiently-small cell area, irrespective of whether it is an SGT-SRAM. As compared with an SRAM made up using a conventional planar transistor, the SGT-SRAM has a higher potential to reduce an SRAM cell area by taking advantage of the feature of the SGT which is formed in a vertical direction.
FIG. 20(a) is a top plan view showing an E/R (enhancement/resistor) type 4T-SRAM described as an embodiment in the Patent Document 1, wherein an SRAM cell comprises four SGTs and two load resistor elements. FIG. 20(b) is a sectional view taken along the line A-A′ in FIG. 20(a).
With reference to the top plan view of FIG. 20(a) and the sectional view of FIG. 20(b), a structure of the SRAM cell will be described below. The SRAM cell comprises two access transistors each formed by a pillar-shaped silicon layer (601a, 601b) and adapted to allow access to the memory cell, two driver transistors each formed by a pillar-shaped silicon layer (602a, 602b) and adapted to drive the memory cell so as to read and write data, and two load resistor elements Ra6, Rb6 each formed by a polysilicon interconnection layer. A lower diffusion layer (607a, 607b, 607) is formed underneath each of the pillar-shaped silicon layers, and an upper diffusion layer 608 is formed in an upper portion of each of the pillar-shaped silicon layers. Further, a gate electrode (606a to 606c) is formed around each of the pillar-shaped silicon layers.
Each of BL6 and BLB6 indicates a bit line, and WL6 indicates a word line. Vcc6 indicates a power supply potential line, and Vss6 indicates a ground potential line. Each of Ma6 and Mb6 indicates a storage node formed by an interconnection layer and adapted to store data therein.    Patent Document 1: JP 2-188966A
In reality, the above SRAM cell involves the following problem. During data reading, data stored in the storage node formed by the interconnection layer (Ma6, Mb6) is read out to the lower diffusion layer (607a, 607b) underneath the access transistor. The readout data is transferred to the bit line (BL6, BLB6) composed of an interconnection layer, via a contact (603a, 603b). In this structure, the contact (603a, 603b) is not an essential component of the SRAM. For example, in a SRAM cell structure where a storage node is formed by the lower diffusion layer underneath the pillar-shaped silicon layer, data stored in the storage node is transferred to the bit line composed of an interconnection layer via a contact formed on a top of the access transistor, so that the contact (603a, 603b) in the above SRAM cell becomes unnecessary. In this case, an SRAM cell area can be reduced by an area of the two contacts.
In the above SRAM cell, the load resistor element (Ra6, Rb6) is formed by the polysilicon interconnection layer, and thereby the formation of the load resistor element leads to a significant increase in SRAM cell area. Thus, as a prerequisite to reducing the SRAM cell area, it is necessary to use a load resistor element capable of minimizing an increase in SRAM cell area.
Moreover, in the above SRAM cell, the word line WL6 has a high resistance because it is made of polysilicon. Thus, in order to achieve an operating speed currently required in an LSI, it is necessary to add one contact to the word line to allow the word line to be lined with an interconnection layer so as to reduce the resistance. This causes a further increase in SRAM cell area.
As above, the SGT-SRAM has a higher potential to reduce an SRAM cell area based on the feature of the SGT which is formed in a vertical direction, as compared with an SRAM made up using a planar transistor. However, considering the above problems, there remains a need for further reducing the SRAM cell area.
In view of the above circumstances, it is an object of the present invention to provide an SGT-based E/R type 4T-SRAM capable of achieving a SRAM cell having a smaller area.